Nvidia's Vera Rubin Gets HBM4 Greenlight From All Three Memory Giants
Jensen Huang confirms Samsung, SK Hynix, and Micron are all certified for next-gen memory supply, which tells us more about the AI chip market than the chips themselves.
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If you want to understand where AI hardware is heading, sometimes you learn more from supply chain announcements than from architecture papers. Nvidia's confirmation that all three major memory manufacturers (Samsung, SK Hynix, and Micron) have been certified to supply HBM4 for the upcoming Vera Rubin accelerators is, on its face, a procurement story. But it's actually a window into how Nvidia is thinking about the next phase of AI infrastructure, and what constraints they're most worried about.
High Bandwidth Memory, or HBM, has become the critical bottleneck for large-scale AI training. To be precise, the issue isn't raw compute anymore. Modern accelerators have more floating-point operations per second than most workloads can saturate. The constraint is memory bandwidth: how quickly you can feed data to those compute units. HBM stacks memory dies vertically and connects them with through-silicon vias, achieving bandwidth figures that would have seemed absurd a decade ago. HBM3e, the current generation, delivers around 1.2 TB/s per stack. HBM4 is expected to push that to 2 TB/s or beyond.
Nvidia's Vera Rubin architecture, announced as the successor to Blackwell, is designed around HBM4 from the ground up. The architecture is expected to ship in 2026, though Nvidia has been characteristically vague about exact timelines. What we do know is that memory bandwidth will be even more central to Vera Rubin's performance story than it was for previous generations.
The news here, confirmed by Bloomberg, is that Jensen Huang has publicly stated all three memory giants are now certified suppliers. This is notable because HBM4 certification is genuinely difficult. The manufacturing tolerances are extreme, the testing requirements are extensive, and historically, not all vendors have passed Nvidia's qualification process for each generation.
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SK Hynix has been the dominant HBM supplier for Nvidia's AI accelerators, with Samsung and Micron playing catch-up. Samsung in particular has struggled with yield issues on advanced HBM products. The fact that all three are now certified suggests either that the technology has matured enough that manufacturing differences matter less, or that Nvidia is deliberately diversifying its supply base. Probably both, actually.
It's worth noting that "certified" doesn't mean "shipping at scale." Certification is a necessary but not sufficient condition for being a major supplier. The actual allocation of orders will depend on yield, pricing, and capacity. We don't have visibility into those contracts.
I know I'm being picky here, but the connection to robotics isn't obvious and deserves spelling out. The immediate applications of Vera Rubin will be datacenter AI training, not robots. But the memory bandwidth constraints that HBM4 addresses are directly relevant to the kinds of models that power robotic systems.
Large vision-language-action models, the kind that companies like Physical Intelligence and Figure are betting on, require massive memory bandwidth during both training and inference. During training, you need to move enormous batches of video, proprioceptive data, and action labels through the network. During inference, especially for real-time control, you need low-latency access to model weights that may be hundreds of billions of parameters.
The current generation of embodied AI models is constrained by what can run on edge hardware with limited memory bandwidth. As HBM4 becomes available in datacenter accelerators, it enables training of larger, more capable foundation models. Those models can then be distilled or quantized for edge deployment, but the ceiling for capability is set by what you can train in the datacenter.
There's a second-order effect too. Nvidia's RTX Spark, their new consumer PC chip announced recently, represents an attempt to bring more AI capability to local devices. The memory architectures developed for HBM4 will eventually trickle down to consumer and embedded products, though the timeline for that is unclear. We're probably looking at 3-5 years before HBM4-derived memory appears in anything you'd put on a robot.
What I find most interesting about this announcement is what it reveals about Nvidia's risk calculus. For the past few years, SK Hynix has been the de facto monopoly supplier for cutting-edge HBM to Nvidia. That's a precarious position for a company building the infrastructure for a trillion-dollar AI buildout.
By certifying all three vendors, Nvidia gains negotiating leverage and supply resilience. If Samsung's yields improve (and they've been investing heavily in their HBM4 process), they could take significant market share. If geopolitical tensions affect any single supplier, Nvidia has alternatives. This is supply chain 101, but it's been surprisingly absent from Nvidia's HBM strategy until now.
The flip side is that this certification process likely required Nvidia to share detailed specifications and testing protocols with all three vendors. That's intellectual property leakage, in a sense. It also means competitors like AMD, who are developing their own HBM4-based accelerators, may benefit from the improved manufacturing capabilities across the industry.
Several things remain unclear from the available reporting. First, we don't know the actual capacity commitments from each vendor. Certification is not allocation. Nvidia could certify Samsung while still buying 80% of their HBM4 from SK Hynix.
Second, the timeline for volume production is fuzzy. HBM4 is expected in 2025-2026, but "expected" does a lot of work in that sentence. Memory manufacturing has a history of delays, and HBM4's complexity makes it particularly susceptible to yield problems.
Third, and this is the question I'd most want answered, what's the actual bandwidth improvement we'll see in practice? The theoretical specs for HBM4 are impressive, but real-world performance depends on how well the memory controller can utilize that bandwidth. Nvidia's track record here is strong, but it's too early to say whether Vera Rubin will fully saturate HBM4's capabilities.
The research community would benefit from more transparency about how memory bandwidth constraints actually affect model training. There's a lot of folklore about what's "memory-bound" versus "compute-bound," but rigorous measurements are rare. Papers like the original Megatron-LM work from Nvidia's research team touched on this, but we need updated analysis for current model scales.
For robotics specifically, I'd want to see benchmarks that measure how memory bandwidth on inference hardware affects real-time control performance. If you're running a 7B parameter VLA model on a robot, what's the relationship between memory bandwidth and achievable control frequency? This probably varies by architecture, but I haven't seen systematic studies.
The supply chain diversification is probably good for the industry overall. Competition tends to drive down prices and improve reliability. But it also means the HBM market is about to get more complicated, with three vendors competing on specs, yields, and pricing. That complexity will filter through to everyone building AI hardware, including the robotics companies that are increasingly dependent on these supply chains.
(A methodological note: this analysis is based on limited public reporting. Nvidia's actual supplier agreements are confidential, and the technical details of HBM4 certification are not disclosed. The claims about yield improvements at Samsung are based on industry reporting, not verified data.)
